1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device that has surface electrodes of a multilayer structure and can maintain high withstand voltage.
2. Background Art
Normally in a semiconductor device requiring high withstand voltage, a p-n junction referred to as a guard ring is disposed in the peripheral area of the device region as FIG. 7 shows. By such a structure, an electric field generated by voltage supply can be gradually relaxed toward the end portion of the semiconductor device. Thereby, even if a predetermined reverse direction voltage is supplied to the p-n junction, an avalanche breakdown due to electric field concentration can be prevented.
The above-described guard ring structure is effective to maintain high withstand voltage. However, since the region for forming guard rings in the peripheral area of the semiconductor device is required, the chip size is expanded.
In Japanese Unexamined Patent Publication No. 6-97439, in order to avoid the expansion of chip size, a SIPOS (semi-insulating polycrystalline silicon) reduced surface field structure shown in FIG. 8 is disclosed.
In the above-described conventional structure shown in FIG. 7, in order to maintain a desired high withstand voltage, the chip size of a semiconductor chip is expanded, and chip costs are elevated. In the structure shown in FIG. 8, the manufacturing process is complicated, and chip costs are elevated. Specifically, in any of the above-described conventional art, there was a problem wherein chip costs are elevated to maintain a desired high withstand voltage.